EEPROM memory, which recently celebrated its 50th birthday, continues to defy obsolescence. Despite its age, EEPROM remains a mature, reliable, and affordable technology for many electronic systems.

The future of AI compute is being built on Arm. AI continues to transform every major market — from the largest datacenters to the smallest devices, such as earbuds — intensifying the demands on ...

HSINCHU, Taiwan, R.O.C., May 13, 2025 – The TSMC (TWSE: 2330, NYSE: TSM) Board of Directors today held a meeting, which passed the following resolutions: ...

I am delighted to share my technical insights into RISC-V in this article to inspire and prepare the next generation of chip designers for the future of the open era of computing. If you understand ...

This paper presents functional coverage analysis automation and an approach to scale down overall simulation time. It is well known that functional verification of configurable IP cores is a real ...

By Aishwary Dadheech, Technical Lead, Kapil Saxena, Delivery Manager, Sandeep Jain, Technical Lead ()While developing large-sized chips, “divide & conquer” techniques are used. This involves ...

Static Timing Analysis (STA) is a key factor to validate while manufacturing a chip, where each design must go for setup and hold validation. In today’s era, technology nodes are shrinking and ...

This paper presents a new interface between the two main chips typically found in Wireless LAN (WLAN) devices: the digital baseband part (BB) and the radio transceiver part (RF). This interface is a ...

RISC-V is gaining attention throughout the semiconductor industry. It offers the lure of an open-source solution that anyone can leverage to create their own CPU or custom accelerator. Of course, dig ...

The latest DDR4 SDRAM memory standard offers significant performance benefits for SoC designers. Graham Allan, senior product marketing manager for DDR at Synopsys, discusses some of the challenges ...

With advanced technology nodes, the SoCs are growing in density and gate count. This creates challenges regarding the testability, and more importantly, the test cost. The design complexity and size ...

RISC-V is a general-purpose license-free open Instruction Set Architecture [ISA] with multiple extensions. It is an ISA separated into a small base integer ISA, usable as a base for customized ...