A 60-GS/s 7b 64-way time interleaved (TI) analog-to-digital converter (ADC) with analog front end (AFE) is described. The presented converter features a non-binary partial loop unrolled (LU) SAR ...

This article presents a 1.75-GS/s single-channel 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) that is based on loop-unrolled architecture with N-comparators for ...